Title :
A ratioless and biasless static CMOS level shifter
Author :
Pouliquen, Philippe O.
Author_Institution :
Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA
fDate :
May 30 2010-June 2 2010
Abstract :
A CMOS level shifter is presented that has no static power dissipation (biasless) and does not rely on MOS device sizing for basic operation (ratioless). Propagation delays for fabricated circuits are presented over a supply range of 5.0 Volts to 0.8 Volts. The proposed level shifter is intended for Scalable CMOS digital libraries and low-power automated test equipment.
Keywords :
CMOS logic circuits; automatic test equipment; delay circuits; logic gates; CMOS logic gates; MOS device sizing; biasless static CMOS level shifter; fabricated circuits; low-power automated test equipment; propagation delays; scalable CMOS digital libraries; static power dissipation; voltage 5.0 V to 0.8 V; CMOS logic circuits; CMOS process; Inverters; Logic devices; Logic gates; MOS devices; Power dissipation; Power supplies; Test equipment; Voltage;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537627
