• DocumentCode
    3383745
  • Title

    Fast wire length estimation in obstructive block placement

  • Author

    Li, Shuting ; Yan, Tan ; Takashima, Yasuhiro ; Murata, Hiroshi

  • Author_Institution
    Grad. Sch. of Environ. Eng., Univ. of Kitakyushu, Fukuoka
  • fYear
    2008
  • fDate
    Aug. 31 2008-Sept. 3 2008
  • Firstpage
    654
  • Lastpage
    657
  • Abstract
    IP-reuse can enhance the design productivity only if the design methodology treats the IPs in a proper way. Especially in the floor-planning phase, sensitive IPs should be treated as routing obstacles, which is impossible when the conventional HPWL-based method is used for routing estimation. This paper proposes an obstacle-aware minimum wiring length (MWL) estimation algorithm, based on the theoretical result in [5], through algorithmic improvements and practical approximation. The experimental results suggests that MWL-based estimation is now possible with only few times larger computational cost comparing to the HPWL-based estimation.
  • Keywords
    integrated circuit interconnections; integrated circuit layout; large scale integration; table lookup; directed acyclic graph; fast wire length estimation; lookup table; obstacle-aware minimum wiring length estimation algorithm; obstructive block placement; routing estimation; visibility graph; Approximation algorithms; Computational efficiency; Computational geometry; Design engineering; Design methodology; Phase estimation; Pins; Productivity; Routing; Wire; directed-acyclic graph; lookup-table; shortest path; visibility graph;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on
  • Conference_Location
    St. Julien´s
  • Print_ISBN
    978-1-4244-2181-7
  • Electronic_ISBN
    978-1-4244-2182-4
  • Type

    conf

  • DOI
    10.1109/ICECS.2008.4674938
  • Filename
    4674938