A 1.5V 12-b 40 MSamples/s CMOS pipelined ADC

A 12-b 40-MSamples/s low power CMOS pipelined analog-to-digital converter is described. A novel switched-capacitor multiply-by-two amplifier with an accurate gain of two is proposed for pipelined ADC. The proposed architecture requires only one opamp in four phases to generate two effective outputs. It significantly suppresses the gain error due to capacitor-mismatch and also provides a better power efficiency. This ADC design achieves DNL and INL of 0.38LSB and 0.48LSB respectively, while SNDR is 69.5 dB and SFDR is 77.1 dB at an input frequency of 10 MHz. Operating at 40MS/s sampling rate under a single 1.5 V power supply, the power consumption is 76.8 mW in a 0.35 μm CMOS process.