A novel multiplying D/A converter stage with low sensitivity to amplifier gain

A multiplying D/A converter stage incorporating a novel technique for compensating the residual error due to finite amplifier gain is proposed. The scheme is suitable for deep-submicron CMOS technologies and is advantageous compared to the available correlated double sampling techniques because it neither doubles the size of the sampling capacitance, nor requires processing of the same input signal twice for cancelling the residual error at the virtual ground. The conducted behavioral simulations confirm the efficiency of the proposed technique applied to a pipelined A/D converter.