A 12-bit 50-MSPS SHA-less opamp-sharing Analog-to-Digital converter in 65nm CMOS

This paper presents a 12-bit 50-MSPS pipelined Analog-to-Digital converter (ADC) in a 65-nm 1P7M CMOS process. A hybrid time-sharing architecture without Sample-and-Hold Amplifier (SHA) is employed to make a trade-off between the performance and power consumption of the ADC. An SHA-less front-end is adopted, including a matched sampling network to considerably reduce aperture error between a 2.5-bit Multiplying Digital-to-Analog Converter (MDAC) and a Sub-Analog-to-Digital converter (SUBADC). Some efforts to optimize operational amplifier (opamp) are also made. Simulation results show that the ADC achieves 83.2-dB SFDR and 73.4-dB SNDR for input signal up to Nyquist range. The ADC consumes 26.6mW at sampling rate of 50MHz from 1.2-V supply voltage.