A technique to reduce the impact of hysterisys in ΣΔ analog to digital converters

This paper deals with dynamic latch hysterisys and its effects on ΣΔ modulators. It sheds light on the difference between its impact on low pass and high pass modulators. It also presents a technique to reduce its effect on low pass ΣΔ modulators. This technique was tested using a 2^nd order feed forward ΣΔ modulator. The employed dynamic latch was designed in a 1.2 V 65 nm CMOS technology. It has an hysterisys of 27 mv at 220 MHz. A Signal to Noise Ratio improvement of 9 dB was achieved using the proposed technique compared to the classical implementation.