• DocumentCode
    3384123
  • Title

    A timing-perspective study on the wire model in placement

  • Author

    Liu, Liu ; Lu, Yongqiang ; Zhou, Qiang

  • Author_Institution
    Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
  • fYear
    2011
  • fDate
    25-28 Oct. 2011
  • Firstpage
    910
  • Lastpage
    913
  • Abstract
    Timing-driven placement has been studied for decades. Many algorithms use traditional wire-length-metric wire models and formulations to add timing driven strategies. Few works try to explore the timing potentials from the wire model of placement. Especially in the current sub-45nm era, two nets with the same wire length possibly vary distinctly from the timing property. In this paper, we explore several factors that affect a net´s worst delay and average delay in addition to the tradition interconnect wire condition. We hope to employ them in future timing-driven placement. Theoretic analysis and experimental verification are provided as well.
  • Keywords
    integrated circuit interconnections; integrated circuit layout; timing; wires (electric); average delay; interconnect wire condition; timing driven strategy; timing-driven placement; timing-perspective study; wire-length-metric wire model; worst delay; Capacitance; Wideband; Delay; Distance; Driver; Net Model; Sink; Timing Driven;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ASIC (ASICON), 2011 IEEE 9th International Conference on
  • Conference_Location
    Xiamen
  • ISSN
    2162-7541
  • Print_ISBN
    978-1-61284-192-2
  • Electronic_ISBN
    2162-7541
  • Type

    conf

  • DOI
    10.1109/ASICON.2011.6157353
  • Filename
    6157353