A CMOS hysteresis undervoltage lockout with current source inverter structure

This paper describes a simple architecture and low power consumption undervoltage lockout (UVLO) circuit with hysteretic threshold. The UVLO circuit monitors the supply voltage and determines whether or not the supply voltage satisfies a predetermined condition. The under voltage lockout circuit is designed based on CSMC 0.5um CMOS technology, utilizing a relatively few amount of circuitry. It is realized with a current source inverter. The threshold voltage is determined by the W/L ratio of current source inverter and resistor in reference generator. The hysteresis is realized by using a feedback circuit to overcome the bad disturbance and noise rejection of the single threshold. Hysteretic threshold range is 40mV. The quiescent current is about 1uA at 3V supply voltage,while the power of circuit consumes only 3uW.