DocumentCode
3384254
Title
A 6mW 480MHz continuous time ΣΔ modulator with 65dB DR over 5MHz bandwidth in 65nm CMOS
Author
Altun, Oguz ; Fayed, Ayman ; Byrd, Russell ; Hezar, Rahmi ; Chandra, Gaurav ; Gomez, Gabriel
Author_Institution
Nanometer Analog Integration Group, Texas Instrum. Inc., Dallas, TX, USA
fYear
2010
fDate
May 30 2010-June 2 2010
Firstpage
3989
Lastpage
3992
Abstract
A second order, single-bit CT ΣΔ ADC with 480MHz sampling frequency and 5MHz input signal bandwidth is presented. The ADC achieves 65dB DR in 65nm standard digital CMOS technology. The proposed implementation has a highly optimized quantizer, feedback path and clock circuitry leading to 4mA of current consumption and 0.11mm2 of area. Figure of Merit for the design is 0.478pJ/conv.
Keywords
CMOS digital integrated circuits; analogue-digital conversion; delta-sigma modulation; integrated circuit design; bandwidth 5 MHz; clock circuitry; continuous time ΣΔ modulator; current 4 mA; digital CMOS technology; feedback path; figure of merit; frequency 480 MHz; optimized quantizer; power 6 mW; sampling frequency; second-order single-bit CT ΣΔ ADC; size 65 nm; Bandwidth; Baseband; CMOS technology; Clocks; Costs; Energy consumption; Sampling methods; Voltage; WiMAX; Wideband;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location
Paris
Print_ISBN
978-1-4244-5308-5
Electronic_ISBN
978-1-4244-5309-2
Type
conf
DOI
10.1109/ISCAS.2010.5537650
Filename
5537650
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