A new interpolation technique for TI ΣΔ A/D converters

Time interleaved sigma-delta converter is a potential candidate for multi-mode wideband analog to digital (A/D) converters dedicated for multistandard receivers. However, the interpolation by zeros recquired to compress the useful signal bandwidth at the input of the sigma-delta modulator imposes constraints on the implementation of the analog part leading to a very large die area due to the high value required for the sampling capacitor. This paper proposes a new interpolation technique using extra samples instead of zeros resulting from the oversampling of the input signal. This new technique not only reduces the die area but also the anti-alias filter order. The proposed technique was validated in a 4 channel time interleaved sigma-delta multi-mode A/D converter designed in 1.2 V 65 nm CMOS process.