A 40 Mbps H.264/AVC CAVLC decoder using a 64-bit multiple-issue video parsing coprocessor

In this paper, we describe a programmable CAVLC decoder implemented with a video parsing coprocessor. The video parsing coprocessor is a VLIW processor that issues multiple instructions and supports condition-controlled instructions to efficiently program control intensive algorithms and customized instructions for bit operations and table matching. The complexity of the parsing coprocessor is 92 Kgates logic circuits with 7 KB SRAM and its operating frequency is 200 MHz when synthesized with a 130 nm CMOS technology. The CAVLC decoder, when operated at 192 MHz, can decode a bitstream at the rate of 40 Mbps, which corresponds to the level 4.1 of H.264/AVC full HD 1080p.