New power rail ESD clamp design with current starving technology

A new technique, introducing current starving into power rail ESD design, is presented and verified in this paper. To achieve the turn-on time requirement of the power rail ESD clamp circuit in a certain time, a smaller capacitor value will be permitted by which the current starving is used. Besides, PMOS keeper architecture is adopted in order to achieve low power leakage. Eventually, combining current starving technique with the PMOS keeper, the capacitor value is reduced by about one in ten.