A method to build reconfigurable architectures by extracting common subgraphs

In this paper, we present a novel method to build reconfigurable architectures. Because an RTL description of a circuit can be converted to a data flow graph (DFG), our method is based on graph mining which aims to extract the common subgraphs among different benchmarks. A tool flow is proposed to convert benchmarks to data flow graphs and extract the common subgraphs. Benchmarks in the field of Error Checking and Correcting (ECC) are selected in the experiment to demonstrate that our method is correct and practical.