DocumentCode
3384459
Title
A high-efficiency reconfigurable 2-D Discrete Wavelet Transform engine for JPEG2000 implementation on next generation digital cameras
Author
Zhao, Xin ; Ying Yi ; Erdogan, Ahmet T. ; Arslan, Tughrul
Author_Institution
Sch. of Eng., Univ. of Edinburgh, Edinburgh, UK
fYear
2010
fDate
27-29 Sept. 2010
Firstpage
109
Lastpage
112
Abstract
In this paper, we present a high-efficiency reconfigurable lifting-based 2-D Discrete Wavelet Transform (DWT) engine targeting next generation digital cameras. The engine is implemented on a newly emerging Dynamically Reconfigurable (DR) processor architecture that offers superior performance advantages on mobile devices. The 2-D DWT engine can be reconfigured for both 5/3 and 9/7 modes. The scanning pattern of DWT is modified in order to better adapt the JPEG2000 standard. Vector Operations (VO) with Single Instruction Multiple Data (SIMD) techniques are introduced to explore expected system performance improvements, while the architecture can be easily reconfigured between different working modes. Simulation results demonstrate that the resulting 2-D DWT architecture provides high throughput that reaches up to 53 fps for a 2048×1024 image, which shows its advantage compared to some FPGA implementations.
Keywords
cameras; discrete wavelet transforms; image coding; parallel processing; 2D DWT architecture; JPEG2000 implementation; JPEG2000 standard; dynamically reconfigurable processor architecture; high-efficiency reconfigurable 2D discrete wavelet transform engine; mobile devices; next generation digital cameras; reconfigurable lifting; single instruction multiple data; vector operations; Discrete wavelet transforms; Field programmable gate arrays; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference (SOCC), 2010 IEEE International
Conference_Location
Las Vegas, NV
ISSN
Pending
Print_ISBN
978-1-4244-6682-5
Type
conf
DOI
10.1109/SOCC.2010.5784730
Filename
5784730
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