Integration of high-level synthesis in ESL platform modeling by automated generation of protocol adapters

In this paper we present an approach for integrating IP components into a general system-level simulation environment by generating tailor-made interfaces and protocol adaptors. With the same methodology we integrate modules modeled for a certain high-level synthesis tool. For modeling systems-on-chip (SoC) interconnects e.g. buses at transaction level we use a generic communication architecture. An essential benefit of our approach is the capability for automatic adaptor generation by mapping component protocols onto a generic protocol which handles communication data and timing. For an independent system integration flow we use the standardized IP exchange format IP-XACT with protocol specific extensions as input for the generation process. In this context we introduce our generic architecture model for component integration in SystemC TLM 2.0 as well.