DocumentCode :
3384519
Title :
NBTI-aware statistical timing analysis framework
Author :
Han, Sangwoo ; Kim, Juho
Author_Institution :
Dept. of Comput. Sci. & Eng., Sogang Univ., Seoul, South Korea
fYear :
2010
fDate :
27-29 Sept. 2010
Firstpage :
158
Lastpage :
163
Abstract :
Negative bias temperature instability (NBTI) has become a major factor of reliability. In this paper, we proposed a simple analytical model to predict the degraded delay distribution due to NBTI and process variation. Using our NBTI and variation-aware timing analysis framework, accurate degraded gate delay is computed without tedious simulation. Moreover, conventional variation-aware design techniques can apply to develop a reliable circuit design using our model.
Keywords :
circuit reliability; logic circuits; statistical analysis; NBTI-aware statistical timing analysis; circuit design reliability; degraded delay distribution; negative bias temperature instability; variation-aware timing analysis; Aging; Delay; Gaussian distribution; Integrated circuit modeling; Logic gates; Stochastic processes; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOC Conference (SOCC), 2010 IEEE International
Conference_Location :
Las Vegas, NV
ISSN :
Pending
Print_ISBN :
978-1-4244-6682-5
Type :
conf
DOI :
10.1109/SOCC.2010.5784734
Filename :
5784734
Link To Document :
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