Title :
Design and performance considerations for an on-chip jitter analysis system
Author :
Erb, Stefan ; Pribyl, Wolfgang
Author_Institution :
Inst. of Electron., Graz Univ. of Technol., Graz, Austria
fDate :
May 30 2010-June 2 2010
Abstract :
In this paper we present an accurate jitter analysis method for use with built-in jitter measurement systems in serial high-speed communications. The method is based on the analysis of jitter distributions, and thus suffers from hardware design aspects, such as the amount of collected jitter samples or the timing resolution. Design equations and empirical relations are derived to characterize these key parameters, in order to provide an optimized system performance. This allows the method to be utilized on-chip for production testing or as a design for test structure.
Keywords :
circuit testing; design for testability; jitter; network analysis; network synthesis; built-in jitter measurement systems; design for test structure; jitter distribution analysis; on-chip jitter analysis system; production testing; serial high-speed communications; Design optimization; Equations; Histograms; Performance analysis; Probability distribution; System performance; System-on-a-chip; Tail; Testing; Timing jitter;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537662
