An area efficient asynchronous gated ring oscillator TDC with minimum GRO stages

Author

Hwang, Kyu-Dong ; Kim, Lee-Sup

Author_Institution

Dept. of Electr. Eng., KAIST, Daejeon, South Korea

fYear

2010

fDate

May 30 2010-June 2 2010

Firstpage

3973

Lastpage

3976

Abstract

An 8-bit, 3-stage asynchronous gated ring oscillator (GRO) time-to-digital converter (TDC) is presented. It employs asynchronous techniques to achieve minimum GRO stages. This lead to about 40% to 70% gate count reduction compared to synchronous GRO-TDC. Count-missing, glitch, and unnecessary addition are eliminated. The uncorrupted noise shaping characteristic is obtained. The chip is implemented in a 0.18 μm CMOS technology. It occupies small area (140μm×310μm) and consumes low power (4mW to 13mW).

Keywords

analogue-digital conversion; asynchronous circuits; oscillators; CMOS technology; area efficient asynchronous gated ring oscillator TDC; asynchronous techniques; gate count reduction; minimum GRO stages; size 0.18 mum; synchronous GRO-TDC; time-to-digital converter; uncorrupted noise shaping characteristic; CMOS technology; Counting circuits; Frequency; Noise reduction; Noise shaping; Phase locked loops; Quantization; Ring oscillators; Sampling methods; Working environment noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Conference_Location

Paris

Print_ISBN

978-1-4244-5308-5

Electronic_ISBN

978-1-4244-5309-2

Type

conf

DOI

10.1109/ISCAS.2010.5537663

Filename

5537663