Title :
A novel RSD correction for pipeline ADC
Author :
Fu, Dawei ; HE, Lenian ; Xu, Biye
Author_Institution :
Inst. of VLSI Design, Zhejiang Univ., Hangzhou, China
Abstract :
Redundant signed digit (RSD) correction is widely employed in pipeline ADC. However, conventional RSD correction provides only one redundant bit to correct comparator offset voltage. This paper proposes a novel RSD correction with two redundant bits, which can correct larger offset voltage and improve the linearity of the pipeline stage transfer function. The effect of this RSD correction is verified in TSMC 0.18um 1P6M CMOS process. When the ADC works at 100MS/s conversion frequency and a 10MHz input signal is applied, the simulation result of SFDR is 105.9 dB.
Keywords :
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); redundant number systems; RSD correction; TSMC 1P6M CMOS process; comparator offset voltage; frequency 10 MHz; pipeline ADC; pipeline stage transfer function linearity; redundant signed digit correction; size 0.18 mum; Signal to noise ratio; Switches;
Conference_Titel :
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location :
Xiamen
Print_ISBN :
978-1-61284-192-2
Electronic_ISBN :
2162-7541
DOI :
10.1109/ASICON.2011.6157373
