A novel RSD correction for pipeline ADC

Redundant signed digit (RSD) correction is widely employed in pipeline ADC. However, conventional RSD correction provides only one redundant bit to correct comparator offset voltage. This paper proposes a novel RSD correction with two redundant bits, which can correct larger offset voltage and improve the linearity of the pipeline stage transfer function. The effect of this RSD correction is verified in TSMC 0.18um 1P6M CMOS process. When the ADC works at 100MS/s conversion frequency and a 10MHz input signal is applied, the simulation result of SFDR is 105.9 dB.