A self-timed cyclic redundancy check (CRC) in VLSI

A self-timed approach to implement a cyclic redundancy check (CRC) for the application of telecommunications is described. The approach is oriented toward multiple channel communications. The paper presents a new scheme to handle an asynchronous feedback to implement the CRC engine. This feedback scheme can also be applied to many applications like asynchronous pipelines and digital signal processing (DSP), which contains computations combining successive data values including feedback. At transistor level, differential cascade voltage switch logic (DCVSL), combined with using common transistors and grouping the gates, is exploited to obtain an efficient CRC circuit engine. The detailed simulation results of CRC encoding and decoding are performed for the verification at functional level, and the hardware is verified by SPICE simulation.