Title :
System-level synthesis: From specification to transaction level models
Author :
Gajski, Daniel D.
Author_Institution :
Center for Embedded Comput. Syst., Univ. of California, Irvine, Irvine, CA, USA
Abstract :
With design complexities increasing daily, the multi-core community is entertaining the idea of increasing the level of abstraction to transaction-level modeling (TLM) and design. However, the proper definition, style or semantics of TLM is not clear. Nor is it clear how to synthesize or verify TLMs. In this paper, we will introduce several TLM models and define their semantics. This formalism will allow us to define design decisions and corresponding model transformations that can be used to transform one model into another. These transformations and refinements are the enabler for automatic synthesis and verification on TLM. We will also discuss the algorithms and flow for model transformation according to the OSI network layers and show how to build tools with inputs and outputs at transaction level. We will conclude with preliminary tools and results that promise a productivity gain of several orders of magnitude.
Keywords :
circuit CAD; integrated circuit design; microprocessor chips; open systems; OSI network layers; automatic synthesis; circuit CAD; design complexities; model transformation; specification-transaction level models; system-level synthesis; CADCAM; Computer aided manufacturing; Electronic design automation and methodology; Embedded computing; Humans; Media Access Protocol; Network synthesis; Open systems; Productivity; Streaming media;
Conference_Titel :
Communications, Circuits and Systems, 2009. ICCCAS 2009. International Conference on
Conference_Location :
Milpitas, CA
Print_ISBN :
978-1-4244-4886-9
Electronic_ISBN :
978-1-4244-4888-3
DOI :
10.1109/ICCCAS.2009.5250317