Algorithmic and architectural transformations for low power realization of FIR filters

We present algorithmic and architectural transforms for low power realization of Finite Impulse Response (FIR) filters implemented both in software on programmable DSPs and as hardwired macros. For the programmable DSP based implementation, these transform address power reduction in the program memory address and data busses and also the multiplier. We also propose architectural extensions to support some of these transformations. The transforms for hardwired FIR filters aim at reducing the supply voltage while maintaining the throughput. We also present transforms that reduce the computational complexity of the FIR filter computation and thus achieve power reduction