• DocumentCode
    3384719
  • Title

    Representing topological structures for 3-D floorplanning

  • Author

    Wang, Rehsherr ; Young, Evangeline F Y ; Cheng, Chung-Kuan

  • Author_Institution
    Univ. of California, San Diego, La Jolla, CA, USA
  • fYear
    2009
  • fDate
    23-25 July 2009
  • Firstpage
    1098
  • Lastpage
    1102
  • Abstract
    3-D VLSI circuit is becoming a hot topic because of its potential of enhancing performance, while it is also facing challenges such as the increased complexity on floorplanning and placement. Efficient 3-D floorplan representations are needed to handle the placement optimization in new circuit designs. We review and categorize some state-of-the-art 3-D representations, and propose a twin quaternary tree (TQT) model for 3-D mosaic floorplans, extending the twin binary tree. Differences between 2-D and 3-D mosaic floorplans are discussed and some 3-D properties not existing in 2-D are revealed. Though the efficiency of the twin tree for optimization heuristics is still an open question, insights from the discussions and conclusions can be helpful for 3-D physical design.
  • Keywords
    VLSI; circuit optimisation; integrated circuit layout; network topology; 3D mosaic floorplanning; TQT model; VLSI circuit design; placement optimization; topological structure; twin quaternary tree; Binary trees; Circuit optimization; Circuit synthesis; Design optimization; Encoding; Integrated circuit interconnections; Moore´s Law; Stacking; Tree graphs; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Communications, Circuits and Systems, 2009. ICCCAS 2009. International Conference on
  • Conference_Location
    Milpitas, CA
  • Print_ISBN
    978-1-4244-4886-9
  • Electronic_ISBN
    978-1-4244-4888-3
  • Type

    conf

  • DOI
    10.1109/ICCCAS.2009.5250323
  • Filename
    5250323