FPGA implementation of nonbinary quasi-cyclic LDPC decoder based on EMS algorithm

Low density parity check (LDPC) codes over GF(2^m) show significantly higher performances than binary LDPC codes. However, the hardware complexity and area of the decoder are largely increasing. In this paper, putting the code and decoder design together to consider, we propose a FPGA semi-parallel implementation of extended min-sum (EMS) decoding algorithm for quasi-cyclic low density parity check (QC-LDPC) codes over GF (2^m). According to the regularity of their parity check matrices, QC-LDPC codes can facilitate efficient high-speed parallel decoding. The EMS decoding algorithm greatly reduces the computational complexity of processing units, check node unit (CNU). In addition, the updating calculation of the check node unit and variable node unit (VNU) can be overlapped to decrease the time latency and increase the throughput. Based on these architectures, the (486,972) QC-LDPC code over GF (4) decoder is implemented on Xilinx field programmable gate array (FPGA) Virtex4 XC4VLX160. The result shows that the maximum clock frequency is 131.411 MHz and the throughput is 50 Mb/s for the EMS decoder.