A low-noise WCDMA transmitter with 25%-duty-cycle LO generator in 65nm CMOS

This paper describes a 65nm CMOS low-noise WCDMA transmitter including direct quadrature voltage modulator and 25%-duty-cycle LO generator. In comparison with conventional approaches employing Gilbert mixers, the use of a passive voltage mixer, core of the transmitter, significantly improves the output noise and linearity performance. A divider directly generating 25%-duty-cyle LO is presented to drive the passive voltage mixer. Delivering 2dBm WCDMA output power at 2500 MHz, the transmitter achieves -44dBc ACLR at 5 MHz offset and -64dBc ACLR at 10 MHz offset, respectively. The noise floor at 2 dBm output is -163 dBc/Hz at the frequency offset above 40 MHz. The transmitter consumes a total power of 59 mW.