Throughput estimation for ModelSim simulator tool based HW/SW co-verification system

Efficient and reliable verification system is requested for a system-on-chip (SOC) design before it is committed to production. The intention of the paper is to judge whether our hardware/software (HW/SW) co-verification system can handle SOC verification and provide the necessary performance in terms of co-verification speed and throughput. A finite impulse response (FIR) filter is utilized as a device-under-test (DUT) to compare pure software simulation, ModelSim simulator in this case, and HW/SW co-verification approaches to decide on whether the HW/SW co-verification system can work or not. Experiment result demonstrates the more complicated SOC is, the greater the potential speedup of the co-verification approach over software simulation is. However, the communication between software and hardware in HW/SW co-verification system is a major bottleneck, which may offset the acceleration achieved by moving large computation from software side to hardware side.