DocumentCode
3384839
Title
A high-speed pipeline processor for regional labelling based on a new algorithm
Author
Hattori, Tetsuo
Author_Institution
Inform. & Comput. Sci. Lab., Kagawa Univ., Takamatsu, Japan
Volume
ii
fYear
1990
fDate
16-21 Jun 1990
Firstpage
494
Abstract
A high-speed regional labeling processor which continuously processes images from an image area sensor at the NTSC video rate, i.e., at the speed of 30 images (512×512×8 b/frame)/s is presented. An algorithm implemented in the processor is described. Since this algorithm retains the label´s linkage information in the form of simple linear list structure and not in graph structure, the hardware of the processor is very simple and has been implemented by wired logic alone
Keywords
computer vision; computerised pattern recognition; parallel algorithms; pipeline processing; video signals; NTSC; computer vision; computerised pattern recognition; parallel algorithms; pipeline processor; regional labelling; video rate; Computer vision; Couplings; Hardware; Head; Image processing; Labeling; Pattern analysis; Pattern recognition; Pipeline processing; Space technology;
fLanguage
English
Publisher
ieee
Conference_Titel
Pattern Recognition, 1990. Proceedings., 10th International Conference on
Conference_Location
Atlantic City, NJ
Print_ISBN
0-8186-2062-5
Type
conf
DOI
10.1109/ICPR.1990.119408
Filename
119408
Link To Document