A 0.25dB gain step high linear programmable gain amplifier

Author

Shen, Xiaobin ; Yan, Taotao ; Lu, Yuxiao ; Zhou, Jianjun

Author_Institution

Center for Analog/RF Integrated Circuits (CARFIC), Shanghai Jiao Tong Univ., Shanghai, China

fYear

2011

fDate

25-28 Oct. 2011

Firstpage

1062

Lastpage

1065

Abstract

A 0.25dB gain step high linear and accurate digitally programmable gain amplifier (PGA) is presented in this paper. The PGA consists of a coarse stage PGA, a fine stage PGA and a buffer. The voltage gain of the coarse PGA can be changed from -6dB to 17dB with 1dB steps and has a -3dB bandwidth of 35MHz. In order to optimize the linearity and gain accuracy, a new structure resistor array is proposed to realize the 0.25dB step fine PGA. The fine PGA shows a dB-linear range of 11.75dB (-5.75dB to 6dB) with a gain error of less than 0.09dB. The proposed PGA circuit is designed in a 0.18um CMOS process and the simulation results show that the PGA has the output-referred third-order interception (OIP3) of 39.7dBm and THD of -79.84dB at -1dBV_p-p output voltage, with a current consumption of 2.2mA from a 1.8V supply.

Keywords

amplification; amplifiers; CMOS process; accurate digitally programmable gain amplifier; bandwidth 35 MHz; current 2.2 mA; current consumption; gain -6 dB to 17 dB; gain 0.25 dB; gain accuracy; gain error; gain step high linear programmable gain amplifier; output-referred third-order interception; size 0.18 mum; structure resistor array; voltage 1.8 V; Electronics packaging; MOSFET circuits; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC (ASICON), 2011 IEEE 9th International Conference on

Conference_Location

Xiamen

ISSN

2162-7541

Print_ISBN

978-1-61284-192-2

Electronic_ISBN

2162-7541

Type

conf

DOI

10.1109/ASICON.2011.6157391

Filename

6157391