Title :
Fast and scalable priority encoding using static CMOS
Author :
Maurya, Satendra Kumar ; Clark, Lawrence T.
Author_Institution :
Sch. of Electr., Comput., & Energy Eng., Arizona State Univ., Tempe, AZ, USA
fDate :
May 30 2010-June 2 2010
Abstract :
The design of high speed, compact and low power priority encoder circuits using static CMOS gates is presented. The proposed hierarchical static design has improved delay and power compared to a dynamic domino circuit implementation. For an 8-bit priority encoder design the proposed approach shows 77.1% power dissipation, 63.6% transistor count and 36% delay improvement. The improvement increases with the number of priority encoder bits, with a delay improvement of 41.2% for a 16 inputs design.
Keywords :
CMOS logic circuits; integrated circuit design; logic gates; low-power electronics; transistor circuits; delay improvement; encoder design; hierarchical static design; low power priority encoder circuit; power dissipation; priority encoding; static CMOS gates; transistor count; Application software; Circuits; Delay lines; Design engineering; Design optimization; Encoding; Power engineering and energy; Power engineering computing; Propagation delay; Very large scale integration;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537688
