An improved pattern generation for Built-in Self-test design based on boundary-scan reseeding

Reseeding is an effective method to reduce test redundancy, i.e., to reduce test length in Built-in Self-test (BIST) design. In general reseeding method, the seeds were saved in a ROM, however, bringing about higher hardware overhead. Managed by Test Access Port (TAP) controller, an improved resseding method proposed in this paper adopts boundary scan architecture to reseed the test pattern generation for BIST with the calculated seeds. Simulation and demonstration results based on selected logic circuit and ISCAS´85 benchmark circuits show that the boundary-scan reseeding can work correctly and effectively, that is, the test length can be largely reduced without losing fault coverage, and thereby, the reduction of hardware overhead is achieved as expectedly.