Optimizing buffer usage for Networks-on-Chip design

Networks-on-Chip (NoC) is the promising communication architecture for next generation SoC. The buffer size of on-chip router impacts the silicon area and power consumption dominantly. Optimizing the buffer usage is important for an efficient NoC design. In this paper, we propose an buffer optimization algorithm for application-specific NoC design. More precisely, given the application traffic parameters and performance contraints, the proposed algorithm automatically determine minimal buffer budget and assign the buffer usage for each input port in different routers. The experimental results show that the proposed algorithms can significantly reduced total buffer usage.