Architecture of a multi-slot main memory system for 3.2 Gbps operation

This paper produces new architecture for a high-data rate and high-density main memory system with bidirectional single-ended signaling. An SSTL-II-based structure has been traditionally been used for chip-to-chip interconnections requiring high-speed and high-density for the main memory system. However, this structure is no longer applicable for a high-speed memory system with high-density. By finding an optimum reflection coefficient at the slot position and determining the transmission line impedance, a multi-slot system can be made to act like a point-to-point system. The proposed main memory system shows significantly improved the signal integrity. The simulated jitter and eye openings, including transmission line loss, were improved by 69.9% for writing and 63.0% for reading at 3.2 Gbps.