Title :
SRAM portless bitcell and current-mode reading
Author :
Hamouche, Lahcen ; Allard, Bruno
Author_Institution :
INSA-Lyon, STMicroelectronics, Crolles, France
fDate :
May 30 2010-June 2 2010
Abstract :
SRAM 6T bitcell suffers many limitations in advanced technology nodes among which varaibility issues. Various alternatives have been experimented and the paper focuses the 5T portless bitcell. Read and write operations are operated by varying voltage conditions. The results in have been reviewed in CMOS 32nm and improvements have been provided. The bitcells are arranged in matrix to permit a current-mode read operation as opposed to voltage-based sensing techniques. Thus safety and stability of the bitcell operation is established without constraints on memory periphery. The current-mode operation enables a significant gain in dynamic power consumption. The paper details the portless operation and current-mode reading based an simulation results. A matrix testchip is currently under fabrication in bulk CMOS 32nm.
Keywords :
CMOS integrated circuits; SRAM chips; current-mode circuits; 5T portless bitcell; CMOS; SRAM 6T bitcell; SRAM portless bitcell; advanced technology nodes; bitcell operation; current-mode read operation; current-mode reading; dynamic power consumption; matrix testchip; memory periphery; portless operation; size 32 nm; voltage conditions; voltage-based sensing techniques; CMOS technology; Circuit simulation; Energy consumption; Memory management; Random access memory; Safety; Silicon on insulator technology; Stability; Virtual reality; Voltage;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537704
