Title :
Clocked semi-floating-gate ultra low-voltage current mirror
Author :
Berg, Y. ; Mirmotahari, O. ; Aunet, S.
Author_Institution :
Dept. of Inf., Univ. of Oslo, Oslo
fDate :
Aug. 31 2008-Sept. 3 2008
Abstract :
In this paper we present a low voltage current mirror based on clocked semi-floating-gate transistors used in low-voltage digital CMOS circuits. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage. The offset voltages are used to shift the effective threshold voltage of the evaluating transistors. The proposed current mirror can operate at supply voltages below 200 mV. Two different current mirrors are described; the common gate- and the split gate current mirror. The simulated data presented are obtained using the Spectre simulator provided by Cadence and valid for a 90 nm CMOS process.
Keywords :
CMOS digital integrated circuits; MOSFET; current mirrors; MOS transistors; Spectre simulator; clocked semi-floating-gate transistors; low-voltage current mirror; low-voltage digital CMOS circuits; offset voltages; size 90 nm; threshold voltage; Analog circuits; CMOS logic circuits; CMOS process; CMOS technology; Circuit simulation; Clocks; Logic circuits; Low voltage; Mirrors; Threshold voltage;
Conference_Titel :
Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on
Conference_Location :
St. Julien´s
Print_ISBN :
978-1-4244-2181-7
Electronic_ISBN :
978-1-4244-2182-4
DOI :
10.1109/ICECS.2008.4675034
