Low-voltage SOI CMOS DTMOS/MTCMOS circuit technique for design optimization of low-power SOC applications

Author

Lin, W.C.H. ; Kuo, J.B.

Author_Institution

Dept of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2010

fDate

May 30 2010-June 2 2010

Firstpage

3833

Lastpage

3836

Abstract

This paper reports a 0.5V SOI CMOS dynamic-threshold MOS (DTMOS)/ dual-threshold (MTCMOS) circuit technique for design optimization of low-power SOC applications. Via the DTMOS/non-DTMOS technique for implementing the SOI version of the gate-level dual-threshold static power optimization methodology (GDSPOM), a 16-bit multiplier circuit has been designed, showing a performance with 30% less power consumption as compared to the one designed purely in DTMOS, at a power supply voltage of 0.5V.

Keywords

CMOS integrated circuits; circuit optimisation; integrated circuit design; low-power electronics; multiplying circuits; silicon-on-insulator; system-on-chip; design optimization; dual threshold circuit; dynamic-threshold MOS; gate level dual threshold static power optimization methodology; low power SOC applications; low voltage SOI CMOS DTMOS/MTCMOS circuit technique; multiplier circuit; voltage 0.5 V; word length 16 bit; CMOS logic circuits; CMOS technology; Design optimization; Energy consumption; Leakage current; Logic gates; Low voltage; Power supplies; Threshold voltage; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Conference_Location

Paris

Print_ISBN

978-1-4244-5308-5

Electronic_ISBN

978-1-4244-5309-2

Type

conf

DOI

10.1109/ISCAS.2010.5537713

Filename

5537713