DocumentCode :
3385811
Title :
A Nanowire Array for Reconfigurable Computing
Author :
Beckett, Paul
Author_Institution :
Sch. of Electr. & Comput. Eng., RMIT Univ., Melbourne, VIC
fYear :
2005
fDate :
21-24 Nov. 2005
Firstpage :
1
Lastpage :
6
Abstract :
A fine-grained reconfigurable array based on complementary, dual-gate, fully depleted, silicon on insulator (DGFD-SOI) nanowire transistors is proposed and analyzed. Both low power and reconfigurable operation may be achieved by altering the switching threshold of the array using the back-gate bias on the complementary double-gate transistors. Simulated performance figures are presented for the array when configured into representative circuits and compared with two similar self-assembled molecular arrays. It is shown that SOI nanowire arrays can achieve dense, low-power reconfigurable operation without the overheads of either level restoration or additional gain blocks that may be required by molecular-based systems.
Keywords :
logic design; nanowires; reconfigurable architectures; silicon-on-insulator; transistors; back-gate bias; complementary double-gate transistors; fine-grained reconfigurable array; molecular-based systems; nanowire array; reconfigurable computing; silicon on insulator nanowire transistors; CMOS technology; Fabrication; Integrated circuit interconnections; Logic devices; Manufacturing; Nanoscale devices; Power engineering and energy; Power engineering computing; Silicon on insulator technology; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
TENCON 2005 2005 IEEE Region 10
Conference_Location :
Melbourne, Qld.
Print_ISBN :
0-7803-9311-2
Electronic_ISBN :
0-7803-9312-0
Type :
conf
DOI :
10.1109/TENCON.2005.301252
Filename :
4085362
Link To Document :
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