DocumentCode
3385876
Title
Constructing high-rate scale-free LDPC codes
Author
Zheng, X. ; Lau, F.C.M. ; Tse, C.K.
Author_Institution
Dept. of Electron. & Inf. Eng., Hong Kong Polytech. Univ., Hong Kong, China
fYear
2010
fDate
May 30 2010-June 2 2010
Firstpage
3781
Lastpage
3784
Abstract
Low-density parity-check (LDPC) codes with scale-free (SF) symbol-node degree distribution have been shown to provide very good error performance. When the code rate becomes high, however, there will be a lot of degree-2 symbol nodes in the “pure” SF-LDPC codes. As a consequence, when the codes are constructed by connecting the symbol nodes with the check nodes, many small-size cycles will be formed. Such small-cycles will degrade the error performance of the codes. In this paper, we address the issue by imposing a new constraint on the design of high-rate SF-LDPC codes. We will compare the error rates of the constrained SF-LDPC codes and other optimized LDPC codes.
Keywords
error correction; parity check codes; LDPC codes; code error performance; low density parity check codes; scale-free symbol node degree distribution; AWGN; Biology; Complex networks; Computer science; Constraint optimization; Degradation; Error analysis; Joining processes; Parity check codes; Virtual colonoscopy;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location
Paris
Print_ISBN
978-1-4244-5308-5
Electronic_ISBN
978-1-4244-5309-2
Type
conf
DOI
10.1109/ISCAS.2010.5537734
Filename
5537734
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