• DocumentCode
    3385974
  • Title

    Top-down approach to technology migration for full-custom mask layouts

  • Author

    Apanovich, Z.V.

  • Author_Institution
    Inst. of Inf. Syst., Acad. of Sci., Novosibirsk
  • fYear
    1998
  • fDate
    4-7 Jan 1998
  • Firstpage
    48
  • Lastpage
    52
  • Abstract
    The approach to technology migration presented in this paper is based on a compaction and rerouting strategy. It takes as input the full-chip mask layout hierarchical description (CIF format) and produces as output the mask layout in the target design rules. The applicability of the compaction and rerouting facilities, and the flexibility of the routing layers redistribution between different levels of mask layout hierarchy, are provided by a procedure for mask layout decomposition. The decomposition procedure takes as input any node of the mask layout hierarchical description and extracts the fragments which should be transformed by means of compaction. The size of the extracted fragments is controlled by decomposition parameters. Each extracted fragment is processed by a symbolisation procedure which provides resizing and regeneration of elementary objects such as transistors, contacts and wires. The target mask layout for each fragment is generated by a compaction procedure which is controlled by the constraints extracted during the symbolisation step. The resulting chip mask layout is generated by a routing procedure which is controlled by the data structures (netlist and floorplan) extracted during the decomposition step
  • Keywords
    VLSI; circuit layout CAD; data structures; integrated circuit layout; masks; network routing; CIF format; compaction strategy; data structures; floorplan extraction; full-custom mask layouts; mask layout decomposition; mask layout hierarchical description; netlist extraction; rerouting strategy; routing layers redistribution; symbolisation procedure; technology migration; top-down approach; Compaction; Contacts; Data mining; Data structures; Merging; Pins; Routing; Size control; Wires; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 1998. Proceedings., 1998 Eleventh International Conference on
  • Conference_Location
    Chennai
  • ISSN
    1063-9667
  • Print_ISBN
    0-8186-8224-8
  • Type

    conf

  • DOI
    10.1109/ICVD.1998.646577
  • Filename
    646577