Title :
Verification of processor microarchitectures
Author :
Shen, Jian ; Abraham, Jacob A.
Author_Institution :
Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
Abstract :
This paper develops a new abstraction technique for processor microarchitecture validation. An abstract finite-state machine model is derived directly from the processor HDL description. This model, along with information about the instruction set, is used for validation coverage analysis. We also present automatic test generation algorithms for generating sequences for traversing state transition paths and covering snapshot and temporal events
Keywords :
VLSI; automatic test pattern generation; computer debugging; data structures; digital simulation; finite state machines; graph theory; hardware description languages; high level synthesis; instruction sets; logic testing; microprocessor chips; pattern matching; ATPG algorithms; VHDL description; abstract FSM model; abstraction technique; automatic test generation algorithms; finite-state machine model; instruction set; microarchitecture validation; processor HDL description; processor microarchitectures; snapshot events; state transition paths; temporal events; validation coverage analysis; Automatic testing; Data mining; Formal verification; Hardware design languages; Jacobian matrices; Microarchitecture; Process design; Registers; State-space methods; System testing;
Conference_Titel :
VLSI Test Symposium, 1999. Proceedings. 17th IEEE
Conference_Location :
Dana Point, CA
Print_ISBN :
0-7695-0146-X
DOI :
10.1109/VTEST.1999.766664
