Title :
Implication and evaluation techniques for proving fault equivalence
Author :
Amyeen, M. Enamul ; Fuchs, W. Kent ; Pomer, Irith ; Boppana, Vamsi
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
Efficient identification of fault equivalence is essential for the completeness and efficiency of diagnostic test pattern generation. In this paper, we present new techniques to prove diagnostic fault equivalence. The techniques are based on implication of the faulty values, and functional evaluation at the dominator gate of the fault sites. The experimental results for all ISCAS85 circuits and full scan versions of ISCAS89 circuits show significant improvement compared to previously proposed techniques in both the number of equivalent pairs identified and the time to prove equivalence
Keywords :
automatic test pattern generation; fault diagnosis; identification; integrated circuit testing; integrated logic circuits; logic testing; ATPG; diagnostic fault equivalence; diagnostic test pattern generation; dominator gate; equivalent pairs identification; evaluation techniques; fault sites; Automatic test pattern generation; Circuit faults; Circuit testing; Cities and towns; Contracts; Fault detection; Fault diagnosis; Logic; Redundancy; Test pattern generators;
Conference_Titel :
VLSI Test Symposium, 1999. Proceedings. 17th IEEE
Conference_Location :
Dana Point, CA
Print_ISBN :
0-7695-0146-X
DOI :
10.1109/VTEST.1999.766666
