A new framework for automatic generation, insertion and verification of memory built-in self test units

Author

Zarrineh, Kamran ; Upadhyaya, Shambhu J.

Author_Institution

IBM Corp., Endicott, NY, USA

fYear

1999

fDate

1999

Firstpage

391

Lastpage

396

Abstract

The design and architecture of a memory test synthesis framework for automatic generation, insertion and verification of memory BIST units is presented. We use a building block architecture which results in full customization of memory BIST units. The flexibility and efficiency of the framework are demonstrated by showing that memory BIST units with different architecture and characteristics could be generated, functionally verified and inserted in a short time. Custom memory test algorithms could be loaded in the supported programmable BIST unit and therefore any type of memory test algorithm could be realized

Keywords

automatic testing; built-in self test; formal verification; high level synthesis; integrated circuit testing; integrated memory circuits; memory architecture; automatic generation; automatic insertion; automatic verification; building block architecture; custom memory test algorithms; full customization; memory BIST units; memory architecture; memory built-in self test units; memory test algorithm; memory test synthesis framework; programmable BIST unit; Automatic testing; Built-in self-test; Circuit testing; Computer architecture; Costs; Design automation; Logic testing; Memory architecture; System testing; Time to market;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1999. Proceedings. 17th IEEE

Conference_Location

Dana Point, CA

ISSN

1093-0167

Print_ISBN

0-7695-0146-X

Type

conf

DOI

10.1109/VTEST.1999.766694

Filename

766694