Title :
DSTN sleep transistor sizing with a new approach to estimate the maximum instantaneous current
Author :
Sun, Yu ; Xiao, Li-yi ; Shi, Cong
Author_Institution :
Microelectron. Center, Harbin Inst. of Technol., Harbin, China
fDate :
May 30 2010-June 2 2010
Abstract :
Power gating is one of most effective ways to suppress the leakage power in CMOS digital circuits. In this paper, we propose a new method to estimate the maximum instantaneous current (MIC), and derive an analytical model for the MIC of the clusters in distributed sleep transistor network (DSTN) power-gated circuits. Based on this MIC estimation model, we perform ST sizing in DSTN power-gated circuits. Experimental results show that we have achieved higher precision and less runtime.
Keywords :
CMOS digital integrated circuits; leakage currents; transistors; CMOS digital circuits; DSTN power-gated circuits; DSTN sleep transistor sizing; MIC estimation model; analytical model; distributed sleep transistor network; leakage power; maximum instantaneous current; power gating; Added delay; CMOS digital integrated circuits; CMOS technology; Logic; Microelectronics; Microwave integrated circuits; Sleep; Sun; Switching circuits; Threshold voltage;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537752
