• DocumentCode
    3386562
  • Title

    Floating gate synapses with spike time dependent plasticity

  • Author

    Ramakrishnan, Shubha ; Hasler, Paul ; Gordon, Christal

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
  • fYear
    2010
  • fDate
    May 30 2010-June 2 2010
  • Firstpage
    369
  • Lastpage
    372
  • Abstract
    This paper demonstrates a single transistor synapse that stores a weight in a non-volatile manner, computes a biological EPSP, and also demonstrates biological learning rules such as LTP, LTD and STDP. It also describes a highly scalable architecture of an array of synapses that can implement the described learning rules. Parameters for weight update in a 0.35μm process were extracted and used to predict changes in weight based on the time difference between pre-synaptic and post-synaptic spike times.
  • Keywords
    learning (artificial intelligence); neural nets; LTD; LTP; STDP; biological EPSP; biological learning rules; floating gate synapses; single transistor synapse; spike time dependent plasticity; Biological system modeling; Biology computing; Circuits; Computer architecture; Electrons; Joining processes; Paper technology; Timing; Tunneling; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
  • Conference_Location
    Paris
  • Print_ISBN
    978-1-4244-5308-5
  • Electronic_ISBN
    978-1-4244-5309-2
  • Type

    conf

  • DOI
    10.1109/ISCAS.2010.5537768
  • Filename
    5537768