Gate oxide reliability correlation between test structures and DRAM product chips

Gate oxide reliability of DRAM product is usually predicted from test structures. In order to understand the relevance of these predictions, a correlation to product is needed. For DRAMs the wordline driver circuit is critical because it involves the highest voltage on the chip and the NFETs of this circuit have nearly 100% duty factor. Specially bonded DRAM chips were subjected to a standby stress with the externally applied boosted wordline voltage being above Bum-In conditions. Standard product test and additional current measurements were used to characterize the chips at each readout. Current degradation is used to demonstrate the proper stress. Fails were physically localized to distinguish between possible gate oxide and other fails. No gate oxide fails were found during the stress time, which was longer than the best-case projection from test structures. Circuit related current limitation is unlikely to inhibit breakdown because the wordline driver devices drive large currents in the mA range. Long-term stress data of packaged test structures shows consistent behavior with a 1/Vg-model, which could explain the product stress results.