Title :
Implementation of large-integer hardware multiplier in Xilinx FPGA
Author :
Athow, Jacques L. ; Al-Khalili, Asim J.
Author_Institution :
Dept of Electr. & Comput. Eng., Concordia Univ., Montreal, QC
fDate :
Aug. 31 2008-Sept. 3 2008
Abstract :
Implementation of wide multipliers for high performance is usually performed by the vendor synthesis/place and route software tool. This paper presents a partition algorithm for large integer multipliers with speed as optimization criteria. The generated solution uses built-in high-speed arithmetic blocks available in the current generation of Xilinx FPGA chip. The proposed technique has shown reduction in delay of more than 30% when compared to both Xilinx Coregen and Xilinx Synthesis Tools generated models.
Keywords :
electronic engineering computing; field programmable gate arrays; Xilinx Coregen; Xilinx FPGA; Xilinx Synthesis Tools; built-in high-speed arithmetic; large-integer hardware multiplier; optimization criteria; Adders; Arithmetic; Circuits; Delay; Field programmable gate arrays; Hardware; High performance computing; Logic design; Partitioning algorithms; Routing; DSP48; FPGA; multiplier; partitioning; pipelined architecture;
Conference_Titel :
Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on
Conference_Location :
St. Julien´s
Print_ISBN :
978-1-4244-2181-7
Electronic_ISBN :
978-1-4244-2182-4
DOI :
10.1109/ICECS.2008.4675098
