Title :
Scaling analysis of yield optimization considering supply and threshold voltage variations
Author :
Haghdad, Kian ; Anis, Mohab
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada
fDate :
May 30 2010-June 2 2010
Abstract :
Parametric yield loss has become a significant issue in the design of nanometer integrated circuits (IC). In this paper, the impact of supply (Vdd) and threshold voltage (Vth) variations on the yield loss for the current and future CMOS technologies is investigated. The results demonstrate that, despite the temporary improvement due to the use of high-k dielectric materials and metal gates (HiK+MG), parametric yield and design robustness will remain amongst the major challenges in the future technology generations. Subsequently, design centers in the Vth-Vdd plane are suggested for having more robust and reliable circuits for the nodes. Monte-Carlo simulations using SPECTRE and HSPICE verify the provided results in this work for 90nm to 16nm nodes.
Keywords :
CMOS integrated circuits; Monte Carlo methods; optimisation; power electronics; CMOS technology; HSPICE; Monte Carlo simulation; SPECTRE; design robustness; high k dielectric material; metal gates; nanometer integrated circuit; parametric yield loss; scaling analysis; supply voltage; threshold voltage variation; yield optimization; CMOS technology; Design optimization; Fluctuations; Integrated circuit technology; Integrated circuit yield; Robustness; Space technology; Temperature; Threshold voltage; Uncertainty;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537773
