• DocumentCode
    3386749
  • Title

    Transition tests for high performance microprocessors

  • Author

    Chang, Yi-Shing ; Chakravarty, Sreejit ; Hoang, Hiep ; Thorpe, Nick ; Wee, Khen

  • Author_Institution
    Intel Corp., Santa Clara, CA, USA
  • fYear
    2005
  • fDate
    1-5 May 2005
  • Firstpage
    29
  • Lastpage
    34
  • Abstract
    The scope and need for scan based transition tests in the context of high volume manufacturing testing of microprocessors is discussed. A classification of transition faults for latch based design is presented. Finally, we discuss a silicon experiment to understand the most fundamental issue of scan based transition testing viz. their robustness.
  • Keywords
    fault diagnosis; integrated circuit manufacture; integrated circuit testing; microprocessor chips; high performance microprocessors; high volume manufacturing testing; latch based design; robustness; scan based transition testing; silicon experiment; transition fault classification; transition tests; Automatic test pattern generation; Cost function; Flip-flops; Manufacturing; Microprocessors; Robustness; Semiconductor device modeling; Silicon; Test pattern generators; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 2005. Proceedings. 23rd IEEE
  • ISSN
    1093-0167
  • Print_ISBN
    0-7695-2314-5
  • Type

    conf

  • DOI
    10.1109/VTS.2005.87
  • Filename
    1443395
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3386749