• DocumentCode
    3386775
  • Title

    At-speed transition fault testing with low speed scan enable

  • Author

    Ahmed, Nisar ; Ravikumar, C.P. ; Tehranipoor, Mohammad ; Plusquellic, Jim

  • Author_Institution
    ASIC Product Dev. Center, Texas Instruments India, Bangalore, India
  • fYear
    2005
  • fDate
    1-5 May 2005
  • Firstpage
    42
  • Lastpage
    47
  • Abstract
    With today´s design size in millions of gates and working frequency in gigahertz range, at-speed test is crucial. The launch-off-shift method has several advantages over the launch-off-capture but imposes strict requirements on transition fault testing due to at-speed scan enable signal. A novel scan-based at-speed test is proposed which generates multiple local fast scan enable signals. The scan enable control information is encapsulated in the test data and transferred during the scan operation. A new scan cell, referred to as last transition generator (LTG), is inserted in the scan chains to generate the fast local scan enable signal. The proposed technique is robust, practice-oriented and suitable for use in an industrial flow.
  • Keywords
    delays; fault diagnosis; integrated circuit testing; last transition generator; launch-off-shift method; low speed scan enable; scan enable control information encapsulation; scan-based at-speed testing; test data; transition fault testing; Application specific integrated circuits; Automatic test pattern generation; Circuit faults; Circuit testing; Clocks; Delay; Frequency; Robustness; Signal generators; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 2005. Proceedings. 23rd IEEE
  • ISSN
    1093-0167
  • Print_ISBN
    0-7695-2314-5
  • Type

    conf

  • DOI
    10.1109/VTS.2005.31
  • Filename
    1443397