A bipartition-codec architecture to reduce power in pipelined circuits

Proposes a new bipartition-codec architecture that may reduce the power consumption of pipelined circuits. We treat each output value of a pipelined circuit as one state of a finite-state machine. If the output of a pipelined circuit mainly transitions among just a few states, we can partition the combinational portion of a pipelined circuit into two blocks: the one that contains the few states of high activity is small, and the other (that contains the remainder of low activity) is large. Consequently, the state transitions are confined to the small block most of the time. Then we replace the small block with a codec circuit, which consists of an encoder and a decoder, to reduce the internal switching activity of the block. The encoder minimizes the number of bit changes during state transitions; thus, the switching which propagates into the decoder is reduced considerably. We present experimental results on several MCNC benchmarks and obtain power savings of up to 63.7% by using our new architecture.