DocumentCode
3386861
Title
AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths
Author
Serdar, T. ; Sechen, C.
Author_Institution
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
fYear
1999
fDate
7-11 Nov. 1999
Firstpage
91
Lastpage
97
Abstract
Describes AKORD, a transistor-level and mixed transistor/gate-level placement tool. AKORD has unique layout capabilities that address the digital data path layout problem. In order to improve communication between the placement and routing steps, new post-placement algorithms were developed: a device re-spacing procedure, an optimization procedure for gate contacts, and a procedure which reduces wire crossovers. AKORD dynamically supports: (1) transistor folding without the usage of device libraries that contain variants of the same device; (2) device merging, including information about optimal transistor chain formation; and (3) well area minimization. Experimental results show that the automated layouts are comparable to skilled manual layouts and that the computation times are quite modest.
Keywords
circuit layout CAD; circuit optimisation; integrated circuit layout; integrated logic circuits; logic gates; minimisation; transistors; AKORD; automated circuit layout; computation times; device libraries; device merging; device respacing procedure; digital data path layout problem; gate contact optimization procedure; mixed transistor/gate-level placement tool; optimal transistor chain formation; post-placement algorithms; routing step; transistor folding; transistor-level placement tool; well area minimization; wire crossovers; CMOS logic circuits; Geometry; Libraries; Manuals; Merging; Minimization; Routing; Shape; Switches; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on
Conference_Location
San Jose, CA, USA
ISSN
1092-3152
Print_ISBN
0-7803-5832-5
Type
conf
DOI
10.1109/ICCAD.1999.810628
Filename
810628
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